1. Field of the Invention
The present invention relates to a semiconductor device including a semiconductor capacitor and a method of manufacturing the semiconductor device.
2. Description of the Related Art
A semiconductor capacitor, which is one of the key components of a semiconductor circuit, is incorporated in various kinds of ICs, and semiconductor capacitors having various structures are used. Conventional semiconductor capacitors include planar capacitors. A typical planar capacitor structure and a method of manufacturing the structure are described for a capacitor formed on a P-type semiconductor substrate as an example with reference to sectional views of FIGS. 3A to 3C illustrating manufacturing processes.
First, as illustrated in FIG. 3A, N-type impurities are implanted by ion implantation into a surface of a P-type semiconductor substrate 8, which is then subjected to heat treatment to form a lower electrode layer 9. Next, as illustrated in FIG. 3B, a surface of the lower electrode layer 9 is thermally oxidized to form a capacitor insulating film 10. Next, as illustrated in FIG. 3C, an upper electrode 11 is formed by: depositing a polycrystalline silicon film through CVD or the like on the capacitor insulating film 10; subjecting the polycrystalline silicon film to ion implantation of N-type impurities and heat treatment; and patterning the polycrystalline silicon film into the upper electrode 11. This sums up a typical structure of conventional planar capacitors and a method of manufacturing the structure. Since planar capacitors can be formed at a low cost without difficulty by utilizing a commonly employed manufacturing process for a transistor, they are widely used.
A drawback of planar capacitors is that the capacitance value is unstable because the width of a depletion layer on the surface of the lower electrode layer is varied depending on the input voltage, and the variations in depletion layer width lead to fluctuations in capacitance value.
This drawback is addressed in some of conventional semiconductor capacitors, and PIP (Polycrystalline silicon-Insulator-Polycrystalline silicon) stacked capacitors are one of those semiconductor capacitors. A typical PIP stacked capacitor structure and a method of manufacturing the structure are described with reference to sectional views of FIGS. 4A to 4C illustrating manufacturing processes, taking a capacitor that is formed on a field oxide film as an example.
First, as illustrated in FIG. 4A, a lower electrode 13 is formed by: depositing a polycrystalline silicon film through CVD or the like on a field oxide film 12; subjecting the polycrystalline silicon film to ion implantation of N-type impurities and subsequently to heat treatment; and patterning the polycrystalline silicon film into the lower electrode 13. Next, as illustrated in FIG. 4B, a capacitor insulating film 14 is formed by deposition through CVD on the lower electrode 13. Next, as illustrated in FIG. 4C, an upper electrode 15 is formed by: depositing a polycrystalline silicon film through CVD or the like on the capacitor insulating film 14; subjecting the polycrystalline silicon film to ion implantation of N-type impurities and heat treatment; and patterning the polycrystalline silicon film into the upper electrode 15. This sums up a typical structure of conventional PIP stacked capacitors and a method of manufacturing the structure. Compared to planar capacitors, stacked capacitors show a very small variation in depletion layer width against the input voltage and have a stable capacitance value since the lower electrode and the upper electrode are formed from polycrystalline silicon in which high-concentration impurities are added.
A problem of stacked capacitors lies in how the capacitor insulating film is formed on polycrystalline silicon. Generally speaking, setting the temperature higher in thermal oxidation of polycrystalline silicon yields an oxide film that has a better film quality. On the other hand, in thermal oxidation at a high temperature, heat during the oxidation process diffuses impurities, which can cause a characteristics change and decreased reliability in other devices (such as transistor). It is for this reason that CVD capable of forming an oxide film at a relatively low temperature is commonly used as a method of forming a capacitor insulating film in a PIP stacked capacitor. However, an oxide film formed by CVD is inferior in characteristics to a thermal oxide film formed on single-crystal silicon. This means that PIP stacked capacitors cannot have a thin capacitor insulating film because forming a thin oxide film by CVD causes deterioration in withstand voltage and reliability. PIP stacked capacitors consequently have a drawback in that the capacitance value cannot be increased.
Trench capacitors are one of semiconductor capacitors that have been proposed to address those drawbacks of planar capacitors and stacked capacitors.
A typical trench capacitor structure and a method of manufacturing the structure are described with reference to sectional views of FIGS. 5A to 5C illustrating manufacturing processes, taking a capacitor that is formed on a P-type semiconductor substrate as an example.
First, as illustrated in FIG. 5A, a lower electrode layer 17, which is formed into a lower electrode, is formed by ion implantation of N-type impurities and heat treatment on a P-type semiconductor substrate 16 where trenches have been formed. Next, as illustrated in FIG. 5B, a capacitor insulating film 18 is formed by thermal oxidation on the trench substrate surface where the lower electrode layer 17 has been formed. Next, as illustrated in FIG. 5C, an upper electrode 19 is formed by: depositing and forming a polycrystalline silicon film, which is formed into the upper electrode 19, through CVD or the like on the capacitor insulating film 18; subjecting the polycrystalline silicon film to ion implantation of N-type impurities and heat treatment; and patterning the polycrystalline silicon film. This sums up a typical structure of conventional trench capacitors and a method of manufacturing the structure.
Formation of the lower electrode layer on the trench substrate surface where a plurality of trenches have been formed as illustrated in FIG. 5C permits trench capacitors to suppress or limit an increase in width of a depletion layer, which is generated in a lower electrode layer surface, by adjusting the impurity concentration of the lower electrode layer or by adjusting the aspect ratio of the trenches and the distance between the trenches. Trench capacitors can consequently suppress a change in capacitance value due to a change in input voltage, which is a problem of planar capacitors. Trench capacitors, in which the capacitor insulating film is formed on a single-crystal silicon substrate, can also use thermal oxidation in forming an oxide film, and the capacitor insulating film can thus be formed thin. This means that the capacitance value can be increased, which makes trench capacitors more advantageous than stacked capacitors. Further, trench capacitors can have a large capacitance by adjusting the aspect ratio and number of the trenches.
Trench capacitors, however, are angular at trench openings and trench bottoms, thickness of the capacitor insulating film and the polycrystalline silicon film for the upper electrode formed on the trenches becomes thin around the trench openings and in the corners of the trench bottoms. The resultant drawback is that trench capacitors are susceptible to dielectric breakdown due to field concentration around the trench openings and in the trench bottom corners where the capacitor insulating film and the polycrystalline silicon film are thin, and are accordingly lowered in reliability.
A method that addresses this drawback by rounding trench openings and trench bottoms has been proposed (see JP 07-263692 A, for example). A method involving rounding trench openings and trench bottoms is described with reference to sectional views of FIGS. 6A to 6C illustrating manufacturing processes. While JP 07-263692 A describes a case of forming a MOSFET on a trench substrate, the method involving rounding trench openings and trench bottoms is made applicable by omitting the process of forming source and drain regions and replacing the transistor's gate oxide film with a capacitor insulating film.
A surface of a semiconductor substrate 20 is oxidized. The resultant oxide film on the substrate surface is partially removed and then a trench is formed in the semiconductor substrate 20. Thereafter, a sacrificial oxide film 21 is formed inside the trench by thermal oxidation. The semiconductor substrate 20 in this state is illustrated in section in FIG. 6A. Next, the sacrificial oxide film 21 is removed as illustrated in FIG. 6B. Subsequently, as illustrated in FIG. 6C, the semiconductor substrate surface from which the sacrificial oxide film 21 has been removed is subjected to thermal oxidation at 1,000° C. or higher (for example, 1,215° C.) in an oxygen atmosphere to form an oxide film 22 (gate oxide film in JP 07-263692 A).
According to JP 07-263692 A, trench openings and trench bottoms can be rounded by executing once a process of forming an oxide film by performing thermal oxidation at 1,000° C. or higher in an oxygen atmosphere after trenches are formed and removing the oxide film formed through thermal oxidation, or by repeating the process twice. With the trench openings and trench bottoms rounded, field concentration in the angular portions of the trenches is avoided.
However, the method which requires executing once or twice the process of forming an oxide film at a high temperature of 1,000° C. or higher in an oxygen atmosphere and removing the oxide film in order to round trench openings and trench bottoms has a problem in that the high temperature heat treatment makes the substrate susceptible to damage such as dislocation. Another problem is that the high temperature heat treatment causes re-distribution in an already formed impurity layer and accordingly raises the possibility of increased variation in impurity concentration.